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78m6612 single - phase, dual - outlet power and energy measurement ic data sheet ds_6612_001 rev 2 1 19 - 5348; rev 2; 1/12 description the teridian ? 78m6612 is a highly integrated, single - phase, power and energy measurement and monitoring system- on - chip ( soc) that includes a 32 - bit compute engine (ce), an mpu core, rtc, and f lash. our single con verter technology ? with a 22 - bit delta - sigma adc, four analog inputs, digital temperature compensation, and precision voltage reference supports a wide range of single - phase, dual - outlet power measurement applications with very few external components. with measurement technology leveraged from maxims flagship utility metering ic s , the device offers features including 32 kb of f lash program memory, 2 kb shared ram, three low - power modes with internal timer or external event wake - up, two uarts , i 2 c/ microwire? eeprom i/f, and an in -system programmable f lash. complete outlet measurement unit (omu) and ac power monitor (ac - pmon) firmware is available or can be pre loaded into the ic. a complete array of ice and development tools, programming libraries and reference designs enable rapid development and certification of power and energy measurement solutions that meet the most demanding worldwide electricity metering standards. mpu rtc timers ia va ib xin xout vref v1 tx0 rx0 com0..3 v3.3a v3.3 sys vbat v2.5 vbias seg0..18 gnda gndd seg 24..31/ dio 4..11 seg 34..37/ dio 14..17 ice i 2 c or wire eeprom power fault comparator serial ports osc/pll converter dio, pulse compute engine flash ram voltage ref regulator power supply teridian 78m6612 temp sensor 32 khz live neut ct vb pwr mode control wake-up battery ice_e gndd v3p3d seg 32,33, 38/ice tx1 rx1 optional outlet optional features ? measures each outl et of a duplex rece ptacle with a sin gle ic ? provides complete energy me asurement and communication protocol ca pability in a s ingle ic ? intelligent switch control c apability ? < 0.5 % wh accuracy o ver 2000:1 current ran ge and over te mperature ? exceeds iec 62053 / ansic12.20 s tandards ? voltage r eference < 40 ppm/c ? four sensor in puts C vdd r eferenced ? low ji tter wh and varh pulse test ou t puts (10 khz max ) ? pulse cou nt for pulse outp uts ? line freque ncy co unt for rtc ? digital temperature com pensation ? sag d etection for p hase a and b ? independent 32 - bit compute en gine ? 46 - 64 hz line frequency ra nge with same calib ration ? phase c ompensation ( 7 ) ? battery b ackup for rtc and battery m onitor ? three battery modes w ith w ake - up tim er: brownout m ode (48 a) lcd m ode (5.7 a) sleep m ode (2.9 a) ? energy di splay on main power failu re ? wake - up tim er ? 22 - bit delta - si gma adc ? 8-b it mpu (80515), 1 clock cycle per i nstruction with i ntegrated ice for mpu d ebug ? rtc with temperature co mpensation ? auto - calibration ? hardware w atchdog timer, power - fail mon itor ? lcd d river ( u p to 152 p ixels ) ? up to 18 general - purpose i/ o pi ns ? 32 khz time b ase ? 32 kb flash with s ecurity ? 2 kb mpu xram ? two uarts ? digital i/o pins com patible with 5 v i nputs ? 64 -p in lqfp or 68 -p in qfn p ackage ? rohs - compliant (6/6) lead (pb) - free packages ? complete application firmware available teridian is a trademark and single converter technology is a register ed trademark of maxim integrated products, inc. microwire is a registered trademark of national semiconductor corp. downloaded from: http:///
78m6612 data sheet ds_6612_001 2 rev 2 table of contents 1 hardware description .................................................................................................................... 7 1.1 hardware overview ................................................................................................................. 7 1.2 analog front end (afe) .......................................................................................................... 8 1.2.1 input multiplexer .......................................................................................................... 8 1.2.2 a/d converter (adc) ................................................................................................... 9 1.2.3 fir filter ..................................................................................................................... 9 1.2.4 voltage references ..................................................................................................... 9 1.2.5 te mperature sensor .................................................................................................... 9 1.2.6 battery monitor ............................................................................................................ 9 1.3 digital computation engine (ce) ........................................................................................... 10 1.3.1 real - time monitor ..................................................................................................... 10 1.3.2 pu lse generator ........................................................................................................ 10 1.3.3 data ram (xram) .................................................................................................... 10 1.4 80515 mpu core .................................................................................................................. 11 1.4.1 uarts ...................................................................................................................... 11 1.5 on - chip resources ............................................................................................................... 11 1.5.1 osci llator ................................................................................................................... 11 1.5.2 pll and internal clocks ............................................................................................. 11 1.5.3 real - time clock (rtc) ............................................................................................. 12 1.5.4 temperature sensor .................................................................................................. 12 1.5.5 fl ash memory ........................................................................................................... 12 1.5.6 optical interface ........................................................................................................ 13 1.5.7 digital i/o .................................................................................................................. 13 1.5.8 lcd drivers .............................................................................................................. 16 1.5.9 eeprom interface .................................................................................................... 16 1.5.10 har dware watchdog timer ........................................................................................ 17 1.5.11 test ports (txuxout pin) ........................................................................................ 17 2 functional description ................................................................................................................ 18 2.1 theory of operation .............................................................................................................. 18 2.2 faul t and reset behavior ...................................................................................................... 19 2.2.1 reset mode ............................................................................................................... 19 2.2.2 power fault circuit .................................................................................................... 19 2.3 data flow ............................................................................................................................. 19 2.4 ce/mpu communi cation ...................................................................................................... 20 3 application information ............................................................................................................... 21 3.1 connection of sensors (ct, resistive shunt) ........................................................................ 21 3.2 connecting 5 v devices ........................................................................................................ 22 3.3 te mperature measurement ................................................................................................... 22 3.4 temperature compensation .................................................................................................. 22 3.5 connecting lcds .................................................................................................................. 23 3.6 connecting i 2 c eeproms .................................................................................................... 23 3.7 connecting three - wire eeproms ....................................................................................... 24 3.8 uart0 (tx0/rx0) ................................................................................................................ 24 3.9 uart1 (tx1/rx1) ................................................................................................................ 25 3.10 connecting v1 and reset pins .............................................................................................. 25 3.11 connecting the emulator port pins ........................................................................................ 26 3.12 flash programming ............................................................................................................... 26 3.13 mpu firmware library .......................................................................................................... 26 3.14 crystal oscillator ................................................................................................................... 26 3.15 measurement calibration ...................................................................................................... 27 4 electrical specifications .............................................................................................................. 28 4.1 absolute maximum ratings ................................................................................................... 28 4.2 recommended external components ................................................................................... 29 downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 3 4.3 recommended operating conditions .................................................................................... 29 4.4 performance specifications ................................................................................................... 30 4.4.1 input logic levels ..................................................................................................... 30 4.4.2 output logic levels ................................................................................................... 30 4.4.3 power - fault comparator ........................................................................................... 30 4.4.4 battery monitor .......................................................................................................... 31 4.4.5 supply current .......................................................................................................... 31 4.4.6 v3p3 d switch ........................................................................................................... 31 4.4.7 2.5v voltage regulator ............................................................................................. 32 4.4.8 low power voltage regulator ................................................................................... 32 4.4.9 crystal oscillator ....................................................................................................... 32 4.4.10 v ref, vbias ............................................................................................................ 33 4.4.11 lcd drivers .............................................................................................................. 33 4.4.12 adc converter, v3p3a referenced .......................................................................... 34 4.4.13 uart1 interface ........................................................................................................ 34 4.4.14 temperature sensor .................................................................................................. 34 4.5 ti ming specifications ............................................................................................................ 35 4.5.1 ram and flash memory ............................................................................................ 35 4.5.2 flash memory timing ................................................................................................ 35 4.5.3 eeprom interface .................................................................................................... 35 4.5.4 reset and v1 .......................................................................................................... 35 4.5.5 rtc .......................................................................................................................... 35 5 packaging .................................................................................................................................... 36 5.1 64 - pin lqfp package .......................................................................................................... 36 5.1.1 pinout ........................................................................................................................ 36 5.1.2 package outline (lqfp 64) ....................................................................................... 37 5.1.3 recommended pcb land patte rn for the lqfp - 64 package ..................................... 38 5.2 68 - pin qfn package ............................................................................................................ 39 5.2.1 pinout ........................................................................................................................ 39 5.2.2 package outline ........................................................................................................ 40 5.2.3 reco mmended pcb land pattern for the qfn - 68 package ...................................... 41 6 pin descriptions .......................................................................................................................... 42 6.1 power/ground pins ............................................................................................................... 42 6.2 analog pins ........................................................................................................................... 42 6.3 digital pins ............................................................................................................................ 43 7 i/o equivalent circuits ................................................................................................................. 44 8 ordering information ................................................................................................................... 45 9 contact information ..................................................................................................................... 45 revision history .................................................................................................................................. 46 downloaded from: http:///
78m6612 data sheet ds_6612_001 4 rev 2 figures figure 1: ic functional block diagram ..................................................................................................... 6 figure 2: afe block diagram ................................................................................................................... 8 figure 3: connecting an external load to dio pins ............................................................................... 15 figure 4: functions defined by v1 ......................................................................................................... 17 figure 5: voltage, current, momentary and accumulated energy ........................................................... 18 figure 6: mpu/ce data flow ................................................................................................................. 19 figure 7: mpu/ce communication ........................................................................................................ 20 figure 8: resistive voltage divider ........................................................................................................ 21 figure 9: resistive current shunt .......................................................................................................... 21 figure 10: current transformer .............................................................................................................. 21 figure 11: connecting lcds .................................................................................................................. 23 figure 12: i 2 c eeprom connection ...................................................................................................... 23 figure 13: three - wire eeprom connection ......................................................................................... 24 figure 14: connections for the rx0 pin ................................................................................................ . 24 figure 15: voltage divider for v1 ........................................................................................................... 25 figure 16: external components for reset: development circuit (left), production circuit (r ight) ....... 25 figure 17: external components for the emulator interface .................................................................... 26 figure 18: 64 - pin lqfp pinout .............................................................................................................. 36 fi gure 19: 68 - pin qfn pinout ................................................................................................................ 39 downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 5 tables table 1: inputs selected in regular and alternate multiplexer cycles ....................................................... 8 table 2: data/direction registers and internal resources for dio pin groups ....................................... 14 table 3: dio_dir control bit ................................................................................................................. 15 table 4: selectable controls using the dio_dir bits ............................................................................. 16 table 5: absolute maximum ratings ...................................................................................................... 28 table 6: recommended external components ...................................................................................... 29 table 7: recommended operation conditions ....................................................................................... 29 table 8: input logic levels .................................................................................................................... 30 tabl e 9: output logic levels ................................................................................................................. 30 table 10: power - fault comparator performance specifications ............................................................. 30 table 11: power - fault comparator performance specifications ( bme=1) .............................................. 31 table 12: supply current performance specifications ............................................................................ 31 table 13: v3p3d switch performance specifications ............................................................................. 31 table 14: 2.5 v voltage regulator performance specifications .............................................................. 32 table 15: low - power voltage regulator performance specifications ..................................................... 32 table 16: crystal oscillator performance specifications ......................................................................... 32 table 17: vref, vbias performance specifications .............................................................................. 33 table 18: lcd drivers performance specifications ................................................................................ 33 table 19: adc converter performance specifications ........................................................................... 34 table 20: uart1 interface performance specificat ions ......................................................................... 34 table 21: temperature sensor performance specifications ................................................................... 34 table 22: ram and flash memory specifications .................................................................................. 35 table 23: flash memory timing specifications ...................................................................................... 35 table 24: eeprom interface timing ..................................................................................................... 35 table 25: reset and v1 timing ........................................................................................................... 35 table 26: rtc range ............................................................................................................................ 35 table 27: power/ground pins ................................................................................................................ 42 table 28: analog pins ............................................................................................................................ 42 downloaded from: http:///
78m6612 data sheet ds_6612_001 6 rev 2 ia va mux xin xout vref ckadc cktest/ seg19 ce 32 bit compute engine mpu (80515) ce control rx1 / dio1 tx1 / dio2 / wpulse / varpulse reset v1 emulator port ce_busy uart tx rx xfer busy com0..3 vlc2 lcd display driver data 00-7f prog 000-7ff data 0000-ffff prog 0000-7fff 0000-7fff mpu xram (2kb) 0000-07ff digital i/o config 2000-20ff i/o ram ce ram (0.5kb) memory share 1000-11ff rtclk rtclk (32khz) mux_sync ckce ckmpu ck32 ce_e rtm_e lcd_e lcd_clk lcd_mode dio 4.9mhz < 4.9mhz 4.9mhz gndd v3p3a v3p3d vbat volt reg 2.5v to logic v2p5 mpu_div sum_cycles pre_samps equ ckout_e 32khz tmuxout mpu_rstz faultz wake tmux[4:0] configuration parameters gnda vbias cross ck_gen osc (32khz) ck32 ckout_e mck pll vref vref_dis div adc mux ctrl mux_div chop_e equ strt ib mux mux ckfir 4.9mhz rtm seg34 / dio14 .. seg37 / dio17, seg39 / dio19, seg40 / dio20 wpulsevarpulse wpulse varpulse test test mode lcd_mode vlc1 vlc0 lcd_e < 4.9mhz lcd_num dio_r dio_dir lcd_num dio_pv/pw mux_alt seg24 / dio4 .. seg31 / dio11 sdck sdout sdin e_rxtx/seg38 e_tclk/seg33 e_rst/seg32 flash (32kb) flsh66zt v3p3a fir_len fir seg0..18 eeprom interface dio_eex ck_2x eck_dis v3p3d lcd_gen rtc rtc_inc_sec rtc_dec_sec vb vbias memory share seg32,33seg19,38 e_rxtxe_tclk e_rst (open drain) ice_e dio1,2 vref_cal ? adc converter + - vref adc_e rtm_0..3 ce_lctn pls_maxwidth pls_interval pls_inv lcd_blkmap lcd_seg lcd_y sleep lcd_only v3p3sys test mux dio3,dio21 / seg41 (68 pin package only) v3p3d temp vbat vbat vbias optical comp_stat power fault opt_txeopt_txinv opt_rxinv opt_rxdis mod opt_txmodopt_fdc ce_lctn (seg13 and seg 14 on 68 pin package only) figure 1 : ic functional block diagram downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 7 1 hardware description 1.1 hardware overview the teridian 78m6612 single - chip measurement and monitoring ic integrates all the primary ac measurement and control blocks required to implement a solid - state electricity power and energy measurement function . the 78m6618 includes : ? a four - input analog front end (afe) ? a n independent digital computation engine (ce) ? a n 8051 - compatible microprocessor (mpu) which executes one instr uction per clock cycle (80515) ? a precision voltage reference ? a temperature sensor ? lcd drivers ? ram and flash memory ? a real time clock (rtc) ? a variety of i/o pins various current sensor technologies are supported including current transformers (ct), and resistive shunts. in a typical application, the 32 - bi t compute engine (ce) of the 78m6612 sequentially processes the samples from the analog inputs on pins ia, va, ib, vb and performs calculations to measure active energy (wh), reactive energy (varh), a 2 h, and v 2 h for four - quadrant measurement . these measurements are then accessed by the mpu, processed further , and output using the peri pheral devices available to the mpu. in addition to advanced measurement functions, the real time clock function allows the 78m6612 to record time of use (tou) measurement information for multi - rate applications and to time - stamp events . measurements can be displayed on 3.3 v lcd s if desired . flexible mapping of lcd display segments will facilitate utilization of existing custom lcd s . design trade - off between number of lcd segments vs . dio pins can be implemented in software to accommodate various require ments. in addition to the temperature - trimmed ultra - precision voltage reference, the on - chip digital temperature com pensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on meas ure ment and rtc accuracy, e.g. to meet the requirements of ansi and iec standards . temperature - dependent external components such as crystal oscillator, current transformers (cts), and their corresponding signal conditioning circuits can be characteri zed and their correction factors can be programmed to produce measurements with exce ptional accuracy over the indus trial temperature range . a block diagram of the ic is shown in figure 1 . a detailed description of various functional blocks follows. downloaded from: http:///
78m6612 data sheet ds_6612_001 8 rev 2 1.2 analog front end (afe) the afe functions as a data acquisition system, controlled by the mpu. it consists of an input multiplexer, a delta - sigma a/d converter, and a voltage reference. the main signals (ia, va, ib, vb) are sampled and the adc counts obtained are stored in ce dram where they can be accessed by the ce and, if necessary, by the mpu. figure 2 : afe block diagram 1.2.1 input multiplexer the input multiplexer supports up to four input signals that are applied to pins ia, va, ib , and vb of the de vice . addit ionally, using the alternate multiplexer selection, it has the ability to select temperature and the battery voltage . the multiplexer can be operated in two modes: ? during a normal multiplexer cycle, the signals from the ia, ib, va, and vb pi ns are selected. ? during the alternate multiplexer cycle, the temperature signal (temp) and the battery monitor are selected, along with the signal sources shown in table 1 . to prevent unnecessary drainage on the battery, the battery monitor is enabled only with the bme bit (0x2020[6]) in the i/o ram. the alternate multiplexer cycles are usually performed infrequently (e.g. every second or so ) by the mpu . in order to prevent disruption of the voltage tracking pll and voltage allpass networks, va is not replaced in the alt mux selections . table 1 d etails the regular and alternative multiplexer sequences . missing samples due to an alt multiplexer sequence are filled in by the ce. table 1 : inputs selected in regular and alternate multiplexer cycles regular mux sequence alt mux sequence mux state mux state equ 0 1 2 3 0 1 2 3 2 ia va ib vb temp va vbat vb in a typical application, ia and ib are connected to current sensors that sense the current on each branch of the line voltage. va and vb are typically connected to voltage sensors through resistor dividers. the multiplexer control circuit i s clocked by ck32, the 32.768 khz clock from the pll block, and launches with each new pass of the ce program. the duration of each multiplexer state depends on the number of adc samples processed by the fir. ia va mux vref 4.9 mhz vbias cross ck32 vref vref_dis mux ctrl mux_div chop_e equ ib mux mux_alt v3p3a fir_len fir vb vbias vref_cal ? adc converter + - vref adc_e temp vbat fir_done fir_start downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 9 1.2.2 a/d converter (adc) a single delta - sigma a/d converter digitizes the voltage and current inputs to the 78m6612 . the resolution of the adc is configurable to either 21 or 22 bit. at the end of each adc conversion, the fir filter output data is stored into the ce ram location. 1.2.3 fir filter the finite impulse response filter is an integral part of the adc and it is optimized for use with the multiplexer . the purpose of the fir filter is to decimate the adc output to the desired resolution . at the end of each adc conversion, the output data is stored into the ce ram location determined by the multiplexer selection . fir data is stored lsb justified, but shifted left by nine bits. 1.2.4 voltage references the device includes an on - chip precision bandgap voltage reference that incorporates auto - zero techniques . the reference is trimmed to minimize errors caused by component mismatch and drift . the result is a voltage output with a predictable temperature coefficient. 1.2.5 temperature sensor the 78m6612 includes an on - chip temperature sensor implemented as a bandgap reference . it is used to determine the die temperature the mpu reads the temperature sensor output during alternate multiplexer cycles. the primary use of the temperature data is to determine the magnitude of compensat ion required to offset the thermal drift in the system (see section 3.4 temperature compensation ). 1.2.6 battery monitor the 78m6618 also has the ability to measure battery voltage by the adc during alternative multiplexer frames. when set, an on - chip 45 k ? load resistor is applied to the battery and a scaled fraction of the battery voltage is applied to the adc input. battery operating modes are not supported in all firmware libraries. contact maxim support for more info rmation. downloaded from: http:///
78m6612 data sheet ds_6612_001 10 rev 2 1.3 digital computation engine (ce) the ce, a dedicated 32 - bit signal processor, performs the precision computations necessary to accurately measure energy . the ce calculations and processes include: ? multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when multiplied with the constant sample time). ? frequency - insensitive delay cancellation on all four channels (to compensate for the delay bet ween samples caused by the multiplexing scheme). ? 90 phase shifter (for narrowband var calculations). ? pulse generation. ? monitoring of the input signal frequency (for frequency and phase information). ? monitoring of the input signal amplitude (for sag detection). ? scaling of the processed samples based on calibration coefficients. ce code is provided by maxim as a part of the application firmware available. the ce is not programmable by the user. measurement algorithms in the ce code can be customized by maxim upon request. the ce program resides in flash memory. allocated flash space for the ce program cannot exceed 1024 words ( 2 kb). the ce can access up to 2 kb of data ram (xram), or 512 32 - bit data words. the ce is also aided by support hardware to facilitate implementation of equations, pulse counters and accumulators. usage of this hardware is firmware specific. 1.3.1 real - time monitor the ce contains a real - time monitor (rtm), which can be program med to monitor four selectable ce dram locations at full sample rate for system debug purposes . the four monitored locations can be serially output to the tmuxout pin via the digital output multiplexer at the beginning of each ce code pass . the rtm output is clocked by cktest . 1.3.2 pulse generator the ce provides four pulse generators used to output ce status indicators (e.g. sag) directly to designated dio pins. 1.3.3 data ram (xram) the ce and mpu use a single general - purpose data ram (also referred to as xram). when the mpu and ce are clocking at maximum frequency (10 mhz), the ram may be accessed up to four times during each 100 ns interval. these consist of two mpu accesses, one ce access and one spi access. downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 11 1.4 80515 mpu core the 78m6612 includes an 80515 mpu (8 - bit, 8051 - compatible) that processes most instructions in one c lock cycle . using a 5 mhz (4.9152 mhz) clock results in a processing throughput of 5 mips . the 80515 architecture eliminates redundant bus states and implements parallel execution of fetch and execution phases . normally a machine cycle is aligned with a memory fetch, therefore, most of the 1 - byte instructions are performed in a single machine cycle (mpu clock cycle) . this leads to an 8x average performance improvement (in terms of mips) over the intel ? 8051 device running at the same clock frequency. actual processor clocking speed can be adjusted to the total processing demand of the application (measurement calculations, memory management and i/o management). typical power and energy measurement functions based on the resu lts provided by the inter nal 32 - bit compute engine (ce) are available for the mpu as part of maxim s standard library . a standard ansi c 80515 application program library is available to help reduce design cycle. 1.4.1 uart s the 78m6612 includes two uart s (uart0 and uart1) that can be programmed to c ommunicate with a variety of external device s . the uarts are dedicated 2 - wire serial interfaces, which can communicate at rates up to 38,400 bits/s . all uart transfers are programmable for parity enable, parity, 2 stop bits/1 stop bit and xon/xoff option for variable communication baud rates from 300 to 38,400 bps. 1.5 on - chip resources 1.5.1 oscillator the 78m6612 oscillator drives a standard 32.768 khz watch crystal . these crystals are accurate and do not require a high - current oscillator circuit . the 78m6612 oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability. 1.5.2 pll and internal clocks timing for the device is derived from the 32.768 khz oscillator output . on - chip timing functions include : ? the mpu master clock ? a real time clock (rtc) ? t he delta - sigma sample clock . t he two general - purpose counter/timers are contained in the mpu. the adc master clock, ckadc, is generated by an on - chip pll. it multiplies the oscillator output frequency ( ck32) by 150. the ce clock frequency is always ck32 * 150, or 4.9152 mhz, where ck32 is the 32 khz clock . the mpu clock frequency is determined by mpu_div and can be 4.9152 mhz *2 - mpu_div hz where mpu_div varies from 0 to 7 ( mpu_div is 0 on power - up) . this makes the mpu clock scalable from 4.9152 mhz down to 38.4 khz . the circuit also generates a 2x mpu clock for use by the emulator . this 2x mpu clock is not generated when eck_dis is asserted by the mpu. the setting of mpu_div is maintained when the device transitions to brownout mode, but the time base in brownout mode is 28,672 hz. downloaded from: http:///
78m6612 data sheet ds_6612_001 12 rev 2 1.5.3 real - time clock (rtc) the rtc is driven directly by the crystal oscillator . the rtc consists of a counter chain and output registers . the counter chain consists of seconds, minutes, hours, day of week, day of month, month, and year . the rtc is not supported in all firmware libraries. contact maxim support for more information. 1.5.4 temperature sensor the device includes an on - chip temperature sensor for determining the temperature of the bandgap reference . the mpu may request an alternate multiplexer frame containing the temperature sensor output by asserting mux_alt . the primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system (see section 3.4 temperature compensation ). 1.5.5 flash memory the 78m6612 includes 32 kb of on - chip flash memory . the flash memory primarily contains mpu and ce program code . it also contains images of the ce dram, mpu ram, and i/o ram. on power - up, before enabling the ce, the mpu copies these images to their respective locations. the f lash memory is segmented into individually erasable 1024 - byte pages. f lash space allocated for the ce program is limited to 1024 words ( 2 kb). the ce program must begin on a 1 - kb boundary of the f lash address space . flash write procedures the mpu has the ability to write to the f lash memory when the ce is disabled . as an alternative to using flash, a small eeprom can store data without compromises. eeprom int erfaces are included in the d evice. updating i ndividual b ytes in f lash m emory the original state of a flash byte is 0xff (all ones). once a value other than 0xff is written t o a flash memory cell, over writing with a different value usually requires that the cell be er ased first. s ince cells cannot be erased individually, the page has to be copied to ram, followed by a page erase. a fter this, the page can be updated in ram and then written back to the flash memory. flash erase procedures flash erasure is initiated by writing a specific data pattern to spec ific sfr registers in the proper sequence. these special pattern/sequence requirements prevent inadvertent erasure of the flash memory. the mass erase sequence is: 1. write 1 to the flsh_meen bit (sfr address 0xb2[1]. 2. write pattern 0xaa to flsh_erase (sfr address 0x94) . the mass erase cycle can only be initiated when the ice port is e nabled. the page erase sequence is: 1. write the page address to flsh_pgadr (sfr address 0xb7[7:1] . 2. write pattern 0x55 to flsh_erase (sfr address 0x94) . downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 13 1.5.6 optical interface the device includes an interface to implement an ir/optical port on uart1 . the pin tx1 is designed to directly drive an external led for transmitting data on an optical link . the pin rx1 is designed to sense the input from an external photo detector used as the receiver for the optical link . the ir/optical interface is not supported in all firmware libraries. contact maxim support for more information. 1.5.7 digital i/o the device includes up to 18 pins (qfn 68 package) or 1 6 pins (lqfp 64 package) of general purpose digital i/o . these pins are compatible with 5v inputs (no current - limiting resistors are needed) . some of them are dedicated dio (dio3), some are dual - function that can alternatively be used as lcd drivers (dio4 - 11, 14 - 17, 19 - 21) and some share functions with the optical port (dio1, dio2) . on reset or power - up, all dio pins are inputs until they are configured for the desired direction under mpu control . the pins are configured by the dio registers and by the five bits of the lcd_num register (located in i/o ram) . once declared as dio, each pin can be configured independently as an input or output with the dio_dirn bits . a 3 - bit configuration word, dio_rx , can be used for certain pins, when configured as dio, to indivi dually assign an internal resource such as an interrupt or a timer control . table 2 lists the direction registers and configurability associated with each group of dio pins . table 3 shows the con - figuration for a dio pin through its associated bit in its dio_dir register. tables showing the relationship between lcd_num and the available segment/dio pins can be found in section 3.5 connecting lcds and in section 4.3 i/o description under lcd_num[4:0]. downloaded from: http:///
78m6612 data sheet ds_6612_001 14 rev 2 table 2 : data/direction registers and internal resources for dio pin groups dio x 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 pin no. (64 lqfp) C 5 7 3 C 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 C C 2 0 2 1 pin no. (68 qfn) C 6 0 3 5 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 C C 2 1 2 2 data register C 1 2 3 4 5 6 7 0 1 2 3 C C 6 7 C dio1=p1 (sfr 0x90) direction re gister C 1 2 3 4 5 6 7 0 1 2 3 C C 6 7 C dio_dir1 (sfr 0x91) internal re sources configurable C y y y y y y y y y y y C C C C dio 16 1 7 1 8 1 9 2 0 2 1 2 2 2 3 pin no. (64 lqfp) 22 1 2 C 2 3 4 4 C C C pin no. (68 qfn) 23 1 3 C 2 4 4 7 6 8 data register 0 1 C 3 4 5 C C dio2=p2 (sfr 0xa0) direction re gister 0 1 C 3 4 5 C C dio_dir2 (sfr 0xa1) internal re sources configurable n n C n n n C C downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 15 table 3: dio_dir control bit dio_dir [n] 0 1 dio pin n function input output additionally, if dio6 and dio7 are declared outputs, they can be configured as dedicated pulse outputs (wpulse = dio6, varpulse = dio7) using dio_pw and dio_pv registers . in this case, dio6 and dio7 are under ce control . dio4 and dio5 can be configured t o implement the eeprom interface. if the optical uart is not used, tx1 and rx1 can be configured as dedicated dio pins (dio1, dio2, see section 1.5.6 optical interface ). a 3 - bit configuration word, i/o ram register, dio_rx (0x2009[2:0] through 0x200e[6:4]) can be used for certain pins, when configured as dio, to individually assign an internal resource such as an interrupt or a timer control (see table 2 for dio pins available for this option) . this way, dio pins can be tracked even if they are configured as outputs. tracking dio pins configured as outputs is useful for pulse counting without external hardware. when driving leds, relay coils etc., the dio pins should sink the current into ground (as shown in figure 3 , right), not source it from v3p3d (as sho wn in figure 3 , left) . this is due to the resistance of the internal switch that connects v3p3d to either v3p3sys or vbat . when configured as inputs, the dual - function (dio/seg) pins should not be pulled above v3p3sys in mission and above vbat in lcd and brownout modes . doing so will distort the lcd waveforms of the other pins. this limitation applies to any pin that can be configured as a lcd driver. the control resources selectable for the dio pins are listed in table 4 . if more than one input is connected to the same resource, the resources are combined using a logical or. figure 3 : connecting an external load to dio pins not recommended 78m6612 dio 1 r v3p3 d led v3p3sys 3.3v dgn d vbat dio1 r v3p3d led v3p3sys 3.3v dgnd vbat recommended r led dio 1 v3p3 d v3p3sys dgn d vbat 3.3v recommended r led dio1 v3p3d 78m6612 v3p3sys dgnd vbat 3.3v downloaded from: http:///
78m6612 data sheet ds_6612_001 16 rev 2 table 4 : selectable controls using the dio_dir bits dio_r value resource selected for dio pin 0 none 1 reserved 2 t0 (counter0 clock) 3 t1 (counter1 clock) 4 high priority i/o interrupt (int0 rising) 5 low priority i/o interrupt (int1 rising) 6 high priority i/o interrupt (int0 falling) 7 low priority i/o interrupt (int1 falling) 1.5.8 lcd drivers the device in the 68 - pin qfn package contains 20 dedicated lcd segment drivers in addition to the 18 multi - use pins described above . thus, the device is capable of driving between 80 to 152 pixels of lcd display with 25% duty cycle (or 60 to 114 pixels with 33% duty cycle). at eight pixels per digit, this corresponds to 10 to 19 digits. the device in the 64 - pin lqfp package contains 18 dedicated lcd segment drivers in addition to the 1 7 multi - use pins described above . thus, the device is capable of driving betwee n 72 to 140 pixels of lcd display with 25% duty cycle (or 60 to 105 pixels with 33% duty cycle). at eight pixels per digit, this corresponds to 9 to 17 digits. the lcd drivers are grouped into four commons and up to 38 segment drivers (68 - pin package), o r 4 commons and 35 segment drivers (64 - pin package) . the lcd interface is flexible and can drive either digit segments or enunciator symbols. segment drivers seg18 and seg19 can be configured to blink at either 0.5 hz or 1 hz . the blink rate is controlled by lcd_y . there can be up to four pixels/segments connected to each of these drivers . lcd_blkmap18[3:0] and lcd_blkmap19[3:0] identify which pixels, if any, are to blink. lcd interface memory is powered by the non - volatile supply . the bits of the lcd memory are preserved in lcd and sleep modes, even if their pin is not configured as seg. in this case, they can be useful as general - pur pose non - volatile storage. 1.5.9 eeprom interface the 78m6612 provides hardware support for a n optional two - pin or a three - wire ( - wire) eeprom interface. two - pin eeprom interface the dedicated 2 - pin serial interface communicates with external eeprom devices . the interface is multiplexed onto the dio4 (sck) and dio5 (sda) pins. three - wire ( - wire) eeprom interface a 500 khz 3- wire interface, using sdata, sck, and a dio pin for cs is also available. downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 17 1.5.10 hardware watchdog timer in addition to the basic watchdog timer included in the 80515 mpu, an independent, robust, fixed - duration, watchdog timer (wdt) is included in the device . it uses the crystal oscillator as its time base and must be refreshed by the mpu firmware at least every 1.5 seconds . when not refreshed on time the wdt overflows, and the part is reset as if the reset pin were pulled high, except that the i/o ram bits will be maintained . 4 096 oscillator cycles (or 125 ms ) after the wdt overflow, the mpu will be launched from program address 0x0000. asserting icr_e will deactivate the wdt. t he wdt can also be disabled by tying the v1 pin to v3p3 . of course, this also deactivates v1 power fault detection . since there is no method in firmware to disable the crystal oscillator or the wdt, it is guar anteed that whatever state the part might find itself in, upon wdt overflow, the part will be reset to a known state. figure 4 : functions defined by v1 1.5.11 test ports (txuxout pin) one out of 16 digital or 8 analog signals can be selected to be output on the tmuxout pin . the function of the multiplexer is described in the applicable firmware documentation. v3p3 v3p3 - 400mv v3p3 - 10mv vbias 0v battery modes normal operation, wdt enabled wdt dis- abled v1 downloaded from: http:///
78m6612 data sheet ds_6612_001 18 rev 2 2 functional description 2.1 theory of operation the energy delivered by a power source into a load can be expressed as: = t dt tit v e 0 )( )( the following formula s apply for wide band mode (true rms): ? p = (i (t) * v (t)) ? q = (s 2 C p 2 ) ? s = v * i ? v = ? v (t) 2 ? i = ? i (t) 2 for actual measurement equations, refer to the applicable 78m6612 firmware description document . for some applications , not only voltage and current amplitudes, but also phase angles and harmonic content may change constantly . thus, simple rms measurements are inherently inaccurate . a modern solid - state electricity m easurement ic such as the 78 m6612 functions by emulating the integral operation above, i.e. it processes current and voltage samples through an adc at a constant frequency . as long as the adc resolution is high enough and the sample frequency is beyond the harmonic range of interest , the current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for the momentary energy . summing up the momentary energy quantities over time will result in accumulated energy. figure 5 : voltage , current, momentary and accumulated energy figure 5 shows the shapes of v(t), i(t), the momentary power and the accumulated power, resulting from 50 samples of the voltage and current signals over a period of 20 ms . the application of 240 vac and 100 a results in an accumulation of 480 ws (= 0.133 wh) over the 20 ms period, as indicated by the accumulated power curve. the described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. -500 -400 -300 -200 -100 0 100 200 300 400 500 0 5 10 15 20 current [a] voltage [v] energy per interval [ws] accumulated energy [ws] downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 19 2.2 fault and r eset behavior 2.2.1 reset mode when the reset pin is pulled high , all digital activity stops . the oscillator and rtc module continue to run . additionally, all i/o ram bits are set to their default states . as long as v1, the input voltage at the power fault bl ock, is greater than vbias, the internal 2.5 v regulator continue s to provide power to the digital section. once initiated, the reset mode persist s until the reset timer times out . this occur s in 4 096 cycles of the real time clock after reset goes low, at which time the mpu begin s executing its pre boot and boot sequences from address 00 . 2.2.2 power fault circuit the 78m6612 includes a comparator to monitor system power fault conditions . when the output of the comparator falls (v1 78m6612 data sheet ds_6612_001 20 rev 2 2.4 ce/mpu communication figure 7 shows the functional relationship between the ce and the mpu . the ce is controlled by the mpu via shared registers in the i/o ram and ram . the ce outputs two interrupt signals to the mpu to indicate the ce is actively processing data and the ce is updating data to the output region of the ram . figure 7 : mpu/ce communication mp u c e pulses interrupts display (memory mapped lcd segments) dio eeprom (i2c ) serial (uart0/1) samples var (dio7) w (dio6) varsu m w sum ad c ext_puls e ce_bus y xfer_busy mux ctrl data apulsew apulse r sag control i/o ram (configuration ram) downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 21 3 a pplication information 3.1 connection of sensors (ct, resistive shunt) figure 8 , figure 9 , and figure 10 s how how resistive voltage dividers, resistive current shunts, and current transformers are connected to the voltage and current inputs of the 78m 6612 . figure 8 : resistive voltage divider figure 9 : resistive current shunt figure 10 : current transformer downloaded from: http:///
78m6612 data sheet ds_6612_001 22 rev 2 3.2 connecting 5 v devices all digital input pins of the 78m6612 are compatible with external 5 v devices. i/o pins configured as inputs do not require current - limiting resistors when they are connected to external 5 v devices. 3.3 temperature measurement measurement of absolute temperature uses the on - chip temperature sensor and applying the following formula: n n n t s n t n t + ? = ) )( ( in the above formula , t is the temperature in c, n(t) is the adc count at temperature t, n n is the adc count at 25c, s n is the sensitivity in lsb/c and t n is +25 c. 3.4 temperature compensation temperature coefficients: the internal voltage reference is calibrated during device manufacture. the temperature coefficients tc1 and tc2 are given as constants that represent typical com ponent behavior (in v/c and v/c 2 , respectively). since tc1 and tc2 are given in v/c and v/c 2 , respectively, the value of the vref voltage (1.195v) has to be taken into account when transitioning to ppm/c and ppm/c 2 . this means t hat ppmc = 26.84*tc1/1.195, and ppmc2 = 1374*tc2/1.195). temperature compensation : t he ce provides the bandgap temperature to the mpu, which then may digitally com pensate the power outputs for the temperature dependence of vref. the mpu, not the ce, is entirely in charge of providing temperature compensation . the mpu applies the following formula to determine gain_adj (address 0x12) . in this formula temp_x is the deviation from nominal or calibration temperature expressed in multiples of 0.1c: 23 2 14 2 2 _ 2 _ 16385 _ ppmc x temp ppmc x temp adj gain ? + ? + = in a power and energy measurement unit, the 78m6612 is not the only component contributing to temperature de pendency . a whole range of components (e.g. current transformers, resistor dividers, power sources, filter capacitors) will contribute temperature effects. since the output of the on - chip temperature sensor is accessible to the mpu, temperature - compensation mechanisms with great flexibility are possible (e.g. system- wide temperature correction over the entire unit rather than local to the chip ) . downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 23 3.5 connecting lcds the 78m6612 has an on - chip lcd controller capable of controlling static or multiplexed lcds. figure 11 shows the basic connection for a n lcd. figure 11 : connecting lcds the lcd segment pins can be organized in the following groups: ? seventeen pins are dedicated lcd segment pins (seg0 to seg13, seg16 to seg18). ? four pins are dual - function pins cktest/seg19, e_rxtx/seg38, e_tclk/seg33, and e_rst/seg32. ? fourteen pins are available as combined dio and segment pins seg24/dio4 to seg31/dio11, seg34/dio14 to seg37/dio17, seg39/dio19, and seg40/dio20. ? the qfn - 68 package adds an additional combination pin, seg41/dio21. also adds two additional lcd segment pins, seg13 and seg14. 3.6 connecting i 2 c eeproms i 2 c eeproms or other i 2 c compatible devices should be connected to the dio pins dio4 and dio5, as shown in figure 12 . pull - up resistors of roughly 10 k ? to v3p3d should be used for both scl and sda signals . the dio_eex register in i/o ram must be set to 01 in order to convert the dio pins dio4 and dio5 to i 2 c pins scl and sda . . figure 12 : i 2 c eeprom connection dio4 dio5 78m6612 eeprom scl sda v3p3d 10k 10k dio4 dio5 eeprom scl sda v3p3d 10k 10k segments 78m6612 lcd commons downloaded from: http:///
78m6612 data sheet ds_6612_001 24 rev 2 3.7 connecting three - wire eeproms wire eeproms and other compatible devices should be connected to the dio pins dio4 and dio5, as shown in figure 13 and described below: ? dio5 connects to both the di and do pins of the three - wire device. ? the cs pin must be connected to a vacant dio pin of the 78m6618. ? in order to prevent bus contention, a 10 k ? to resistor is used to separate the di and do signals. ? t he cs and clk pin s should be pulled down with resistor s to prevent operation of the three -w ire device on power - up, before the 78m6618 can establish a stable signal for cs and clk. ? the dio_eex register in i/o ram must be set to 2 (b 10 ) in order to convert the dio pins dio4 and dio5 to wire pins. the - wire eeprom interface is only functional when mpu_div[2:0] = 000. figure 13 : three - wire eeprom connection 3.8 uart0 (tx 0 /rx 0) the uart0 rx 0 pin should be pulled down by a 10 k ? resistor and additionally protected by a 100 pf ceramic capacitor, as shown in figure 14 . figure 14 : connections for the rx 0 pin tx0 rx0 10k 100pf rx tx 78m6612 10k 100pf rx0 tx0 dio4 dio5 eeprom sclk di v3p3d 10k cs dion do 10k dio4 dio5 78m6612 eeprom sclk di v3p3d 10k cs dion do 10k downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 25 3.9 uart1 ( tx 1/ rx 1 ) the tx 1 and rx 1 pins can be used for a regular serial interface (by connecting a rs - 232 transceiver for example), or they can be used to directly operate optical components (for example, an inf rared diode and phototransistor implementing a flag interface ). 3.10 connecting v1 and reset pins a voltage divider should be used to establish that v1 is in a safe range (see figure 15 ) . v1 must be lower than 2.9 v in all cases in order to keep the hardware watchdog timer enabled. a series 5 k ? resistor (r3) and a capacitor to ground (c1) are added for enhanced emc immunity. the parallel impedance of r1 and r2 should be approximately 8 k ? to 10 k ? in order to provide hysteresis for the power fault monitor. figure 15 : voltage divider for v1 even though a functional power and measurement unit will not necessarily need a reset switch, it is useful to have a reset pushbutton switch for prototyping, as shown in figure 16 , left side. the reset signal may be sourced from v3p3sys, or vbat (if a battery is present), or from a comb ination of these sources, depending on the application. for production, the reset pin should be protected by the external components shown in figure 16 , right side . r 1 should be in the range of 100 ? and mounted as closely as possible to the ic. the reset pin can also be directly connected to ground. figure 16 : external components for reset: development circuit (left), production circuit ( right) v3p3 r 2 v1 r 1 r 3 5k c 1 100pf gnd v3p3 r 2 v1 r 1 r 3 5k c 1 100pf gnd r 1 rese t 78m6612 dgn d v3p3d r 2 reset switc h 1k 1nf 10k r 1 dgn d r 2 vbat/ v3p3d reset switc h 1k 1nf 10k r 1 100 r 1 reset 78m6612 dgnd 100 downloaded from: http:///
78m6612 data sheet ds_6612_001 26 rev 2 3.11 connecting the emulator port pins even when the emulator is not used, small shunt capacitors to ground (22 pf) should be used for protection from emi as illustrated in figure 17 . produ ction boards should have the ice_e pin connected to ground. figure 17 : external components for the emulator interface 3.12 flash programming operational or test code can be programmed into the flash memory using either an in - circuit emulator or the flash programmer module (tfp2 ) available from maxim . the flash programming procedure uses the e_rst, e_rxtx, and e_tclk pins. 3.13 mpu firmware library any applications - specific mpu functions mentioned above are available from maxim as a standard ansi c library and as ansi c source code. sample application code using the measurement libr ary is pre - programmed in evaluation kits for the 78m6618 ic and can be pre - programmed into engineering ic samples for system evaluation. application code allows for quick and efficient evaluation of the ic without having to write firmware or having to purchase an in - circuit emulator (ice). a software licensing agreement (sla) can be signed to receive either the source flash hex file for use in a production envir onment or source code and sdk documentation for modification. 3.14 crystal oscillator the oscillator drives a standard 32.768 khz watch crystal . the oscillator has been designed specifically to handle these crystals and is compatible with their high impedance and limited power handling capability . good layouts will have xin and xout shielded from each other. since the oscillator is self - biasing, an external resistor must not be connected across the crystal. e_rst e_rxt x e_tcl k 62 62 6 2 22p f 22p f 22p f lcd segments (optional ) ice_e v3p3d e_rst 78m661 2 e_rxtx e_tclk 62 62 6 2 22p f 22p f 22p f lcd segments (optional ) ice_e v3p3d downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 27 3.15 measurement calibration once the 78m6612 energy m easurement device has been installed in a measurement system, it is typically calibrated . a complete calibration includes the following: ? calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers and signal conditioning components as well as of the internal reference voltage (vref). ? establishment of the reference temperature ( section 3.3 ) for temperature measurement and temperature compensation ( section 3.4 ). the metrology section can be calibrated using the gain and phase adjustment factors accessible to the ce. the gain adjustment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. phase adjustment is provided to compensate for phase shifts introduced by certain types of current sensors or by the effects of reactive power s upplies. due to the flexibility of the mpu firmware, any calibration method, such as calibration based on energy, or current and voltage can be implemented. it is also possible to implement segment - wise calibration (depending on current range) . downloaded from: http:///
78m6612 data sheet ds_6612_001 28 rev 2 4 electrical specifications 4.1 absolute maximum ratings table 5 shows the absolute maximum ranges for the device. stresses beyond absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions ( section 4.3 ) is not implied. exposure to absolute - maximum - rated conditions for extended periods may affect device reliability. all voltages are with respect to gnda. table 5 : absolute maximum ratings supplies and ground pins v3p3sys, v3p3a - 0.5 v to 4.6 v vbat - 0.5 v to 4.6 v gndd - 0.5 v to +0.5 v analog output pins v3p3d - 10 ma to 10 ma , - 0.5 v to 4.6 v vref - 10 ma to +10 ma , - 0.5 v to v3p3a+0.5 v v2p5 - 10 ma to +10 ma , - 0.5 v to 3.0 v analog input pins ia, va, ib, vb, v1 - 10 ma to +10 ma - 0.5 v to v3p3a+0.5 v xin, xout - 10 ma to +10 ma - 0.5 v to 3.0 v all other pins configured as seg or com drivers -1 ma to +1 ma, - 0.5 to v3p3d+0.5 configured as digital inputs - 10 ma to +10 ma, - 0.5 to 6 v configured as digital outputs - 15 ma to +15 ma, - 0.5 v to v3p3d+0.5 v all other pins - 0.5 v to v3p3d+0.5 v temperature and esd stress operating junction temperature (peak, 100 ms ) 140 c operating junction temperature (continuous) 125 c storage temperature - 45 c to +165 c solder temperature C 10 second duration 250 c esd stress on all pins 4 kv stresses beyond absolute maximum ratings may cause permanent damage to the device . these are stress ratings only and functional operation at these or any other conditions beyond those indicated under recommended operating conditions is not implied . exposure to absolute - maximum - rated conditions for extended periods may affect device re liability . all voltages are with respect to gnda. downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 29 4.2 recommended external components table 6: recommended external components name from to function value unit c1 v3p3a agnd bypass capacitor for 3.3v supply . 0.1 20% f c2 v3p3d dgnd bypass capacitor for 3.3v output . 0.1 20% f csys v3p3sys dgnd bypass capacitor for v3p3sys . 1.0 30% f c2p5 v2p5 dgnd bypass capacitor for v2p5 . 0.1 20% f xtal xin xout 32.768 khz crystal C electrically similar to ecs .327 - 12.5 - 17x or vishay xt26t, load capaci tance 12.5 pf . 32.768 khz cxs ? xin agnd load capacitor for crystal (exact value depends on crystal specifications and parasitic capacitance of board). 27 10% pf cxl ? xout agnd 27 10% pf ? depending on trace capacitance, higher or lower values for cxs and cxl must be used . capacitance from xin to gndd and xout to gndd (combining pin, trace and crystal capacitance) should be 35 pf to 37 pf . 4.3 recommended operating conditions table 7: recommended operation conditions parameter condition min typ max unit v3p3sys, v3p3a : 3.3v supply voltage v3p3a and v3p3sys must be at the same voltage normal operation 3.0 3.3 3.6 v battery backup 0 3.6 v vbat no battery externally connect to v3p3sys battery backup brn and lcd modes sleep mode 3.0 2.0 3.8 3.8 v v operating temperature - 40 +85 oc downloaded from: http:///
78m6612 data sheet ds_6612_001 30 rev 2 4.4 p erformance specifications 4.4.1 input logic levels table 8: input logic levels parameter condition min typ max unit digital high - level input voltage ? , v ih 2 v digital low - level input voltage ? , v il 0.8 v input pull - up current, i il e_rxtx, e_rst, cktest other digital inputs vin=0v, ice_e=1 10 10 -1 0 100 100 1 a a a input pull down current, i ih ice_e other digital inputs vin=v3p3d 10 -1 0 100 1 a a ? in battery powered modes, digital inputs should be below 0.3 v or above 2.5 v to minimize battery current. 4.4.2 output logic levels table 9: output logic levels parameter condition min typ max unit digital high - level output voltage v oh i load = 1 ma v3p3d - 0.4 v i load = 15 ma v3p3d - 0.6 v digital low - level output voltage v ol i load = 1 ma 0 0.4 v i load = 15 ma 0.8 v tx1 v oh ( v3p3d - tx1 ) i source =1 ma 0.4 v tx1 v ol i sink =20 ma 0.7 v 4.4.3 power - fault c omp arator table 10 : power - fault comparator performance specifications parameter condition min typ max unit offset voltage : v1-vbias - 20 +15 mv hysteresis current: v1 vin = vbias C 100 mv 0.8 1.2 a response time : v1 + 100 mv overdrive 2 5 10 s wdt disable threshold ( v1- v3p3a ) - 400 - 10 mv downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 31 4.4.4 battery m onitor table 11 : power - fault comparator performance specifications ( bme =1) parameter condition min typ max unit load resistor 27 45 63 k lsb value - does not include the 9 - bit left shift at ce input. fir_len =0 fir_len =1 - 6.0 - 2.6 - 5.4 - 2.3 - 4.9 - 2.0 v v offset error - 200 - 72 +100 mv 4.4.5 s upply current table 12 : supply current performance specifications parameter condition min typ max unit v3p3a + v3p3sys current normal operation, v3p3a=v3p3sys =3.3v mpu_div[1:0] =3 (614 khz ) ckout_e [1:0] =00, ce_en =1, rtm_e =0, eck_dis =1, adc_e =1, ice_e=0 6.1 7.7 ma vbat current - 300 +300 na v3p3a + v3p3sys current vs. mpu clock frequency same conditions as above 0.5 ma/ mhz v3p3a + v3p3sys current, write flash normal operation as above, except write flash at maximum rate, ce_e =0, adc_e =0 9.1 10 ma vbat current ? vbat=3.6v brownout mode, <25c brownout mode, <>5c lcd mode, 25 c lcd mode, over temperature sleep mode, 25 c sleep mode, over temperature 48 65 5.7 2.9 120 150 8.5 15 5.0 10 a a a a a a ? current into v3p3a and v3p3sys pins is not zero if voltage is applied at these pins in brownout, lcd or sleep modes. 4.4.6 v3p3d s witch table 13 : v3p3d switch performance specifications parameter condition min typ max unit on resistance C v3p3sys to v3p3d | i v3p3d | 1 ma 10 on resistance C vbat to v3p3d | i v3p3d | 1 ma 40 downloaded from: http:///
78m6612 data sheet ds_6612_001 32 rev 2 4.4.7 2.5v voltage regulator unless otherwise specified, load = 5 ma. table 14 : 2.5 v voltage regulator performance specifications parameter condition min typ max unit voltage overhead v3p3-v2p5 reduce v3p3 until v2p5 drops 200 mv 440 mv pssr ? v2p5/ ? v3p3 reset=0, iload=0 -3 +3 mv/v 4.4.8 low power voltage r egulator unless otherwise specified, v3p3sys=v3p3a =0 . table 15 : low - power voltage regulator performance specifications parameter condition min typ max unit v2p5 i load =0 2.0 2.5 2.7 v v2p5 load regulation i load =0 ma to 1 ma 30 mv vbat voltage requirement i load =1 ma , reduce vbat until reg_lp_ok=0 3.0 v psrr v2p5 / vbat i load =0 - 50 50 mv/v 4.4.9 crystal oscillator table 16 : crystal oscillator performance specifications parameter condition min typ max unit maximum output power to crystal crystal connected 1 w xin to xout capacitance 3 pf capacitance to dgnd xin xout 5 5 pf pf downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 33 4.4.10 vref, vbias unless otherwise specified, vref_dis =0 . table 17 : vref, vbias performance specifications parameter condition min typ max unit vref output voltage, vnom(25) ta = 22oc 1.193 1.195 1.197 v vref chop step 50 mv vref output impedance vref_cal =1, i load = 10 a, - 10 a 2.5 k vnom definition 1 2 ) 22 ( 1 ) 22 ( ) 22 ( )( 2 tc t tc t vref t vnom ? + ? + = v vref temperature coefficients tc1 tc2 +7.0 - 0.341 v/oc v/c 2 vref aging 2 5 ppm/ year vref(t) deviation from vnom(t) 62 10 )( )( 6 vnom t vnom t vref ? ta = - 40oc to +85oc - 40 +40 ppm/o c vbias voltage ta = 25 oc ta = - 40 oc to 85 oc (- 1%) (- 4%) 1.6 1.6 (+1%) (+4%) v v 1 this relationship describes the nominal behavior of vref at different temperatures. 4.4.11 lcd d rivers the information in table 18 a pplies to all com and seg pins. table 18 : lcd drivers performance specifications parameter condition min typ max unit vlc2 max voltage with respect to vlcd - 0.1 0+.1 v vlc1 voltage, ? bias ? bias with respect to 2*vlc2/3 with respect to vlc2/2 -4 -3 0 +2 % % vlc0 voltage, ? bias ? bias with respect to vlc2/3 with respect to vlc2/2 -3 -3 +2 +2 % % vlcd is v3p3sys in mission mode and vbat in brownout and lcd modes. downloaded from: http:///
78m6612 data sheet ds_6612_001 34 rev 2 4.4.12 adc converter , v3p3a r eferenced fir_len =0, vref_dis =0, lsb values do not include the 9 - bit left shift at ce input. table 19 : adc converter performance specifications parameter condition min typ max unit recommended input range (vin- v3p3a ) - 250 250 mv peak voltage to current crosstalk: ) cos( * 10 6 vcrosstalk vin vin vcrosstalk ? vin = 200 mv peak, 65 hz, on va vcrosstalk = largest measurement on ia or ib - 10 10 v/v thd (first 10 harmonics) 250 mv - pk 20 mv - pk vin=65 hz, 64 kpts fft, blackman - harris window - 75 - 90 db db input impedance vin=65 hz 40 90 k temperature coefficient of input impedance vin=65 hz 1.7 /c lsb size fir_len =0 fir_len =1 357 151 nv/lsb digital full scale fir_len =0 fir_len =1 + 884736 2097152 lsb adc gain error vs %power supply variation 3.3/3 3 100 / 357 10 6 a p v v nv nout in pk ? ? vin=200 mv pk, 65 hz v3p3a=3.0v, 3.6v 50 ppm/% input offset (vi n- v3p3a ) - 10 10 mv 4.4.13 uart 1 i nterface table 20 : uart1 interface performance specifications parameter condition min typ max unit tx1 v oh ( v3p3d - tx1 ) i source =1 ma 0.4 v tx1 v ol i sink =20 ma 0.7 v 4.4.14 temperature sensor table 21 : temperature sensor performance specifications parameter condition min typ max unit nominal sensitivity (s n ) ? t a =25oc, t a =75oc, fir_len = 1 nominal relationship: n(t)= s n *(t -t n )+n n - 2180 lsb/oc nominal (n n ) ? ? 1.0 10 6 lsb temperature error ? ? ?? ? ? ?? ? + ? ? = n n n t s n tn t err ) )(( t a = - 40oc to +85oc tn = 25c - 10 +10 oc ? lsb values do not include the 9 - bit left shift at ce input. ?? n n is measured at t n during calibration and is stored in mpu or ce for use in temperature calculations. downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 35 4.5 timing s pecifications 4.5.1 ram and flash memory table 22 : ram and flash memory specifications parameter condition min typ max unit ce dram wait states ckmpu = 4.9 152 mhz 5 cycles ckmpu = 1.25 mhz 2 cycles ckmpu = 614 khz 1 cycles flash read pulse width v3p3a=v3p3sys=0 brownout mode 30 100 ns flash write cycles - 40 c to +85 c 20,000 cycles flash data retention 25 c 100 years flash data retention 85 c 10 years flash byte writes between page or mass erase operations 2 cycles 4.5.2 flash memory timing table 23 : flash memory timing specifications parameter condition min typ max unit write time per byte 42 s page erase (512 bytes) 20 ms mass erase 200 ms 4.5.3 eeprom i nterface table 24 : eeprom interface timing parameter condition min typ max unit write clock frequency ( i 2 c) ckmpu=4.9152 mhz, using interrupts 78 khz ckmpu=4.9152 mhz, bit - banging dio4/5 150 khz write clock frequency (3 - wire) ckmpu=4.9152 mhz 500 khz 4.5.4 reset and v1 table 25 : reset and v1 timing parameter condition min typ max unit reset pulse fall time 1 s reset pulse width 5 s v1 response time + 100 mv overdrive 10 37 100 s 4.5.5 rtc table 26 : rtc range parameter condition min typ max unit range for date 2000 2255 year downloaded from: http:///
78m6612 data sheet ds_6612_001 36 rev 2 5 packaging 5.1 64 - pin lqfp package 5.1.1 pinout 1 teridian 78m6612-igt 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 31 32 26 27 28 29 30 17 18 19 20 21 22 23 24 25 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 6463 62 61 51 52 53 54 55 56 57 58 59 6049 50 tmuxout tx1/dio2 tx0 seg37/dio17 seg3 v3p3d seg19/cktest seg4seg5 com1 v3p3sys com3 e_rxtx/seg38 gndd com2 seg13 seg12 seg7seg8 seg6 seg36/dio16 seg35/dio15 seg34/dio14 seg2 seg1 seg16 seg0seg9 seg11 seg10 seg27/dio7 seg40/dio20seg26/dio6 seg25/dio5 seg29/dio9 rx0seg31/dio11 resetv2p5 vbat seg24/dio4 seg28/dio8ice_e seg18 seg17 seg30/dio10 e_rst/seg32 e_tclk/seg33va gnddxout test xin v1 vref ia ib v3p3a gnda vb gndd rx1/dio1 seg39/dio19 com0 figure 18 : 64 - pin lqfp pinout downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 37 5.1.2 package o utline (lqfp 64) 11.7 12.3 0.60 typ. 1.40 1.60 11.7 12.3 0.00 0.20 9.8 10.2 0.50 typ. 0.14 0.28 pin no. 1 indicator + note : controlling dimensions are in mm . downloaded from: http:///
78m6612 data sheet ds_6612_001 38 rev 2 5.1.3 recommended pcb land pattern for the lqfp - 64 package x y a g g a x y e e recommended pcb land pattern dimensions symbol description typical dimension e lead pitch 0.5 mm x pad width 0.25 mm y pad length. see n ote . 2.0 mm a 7.75 mm g 9.0 mm note : the y dimension has been elongated to allow for hand soldering and reworking. production assembly may allow this dimension to be reduced as long as the g dimension is maintained. downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 39 5.2 68 - pin qfn package 5.2.1 pinout teridian 78m6612-im gndd e_rxtx/seg38 12 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 5150 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 tx1/dio2 tmuxout dio3 tx0 seg3 v3p3d cktest/seg19 v3p3sys seg4 seg5 seg37/dio17 com0com1 com2 com3 seg0 seg1seg2 seg34/dio14seg35/dio15 seg36/dio16 seg39/dio19 seg6seg7 seg8 seg9 seg10seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 ice_e seg24/dio4 seg25/dio5 seg26/dio6 seg27/dio7 seg28/dio8 seg29/dio9 seg30/dio10 seg31/dio11 seg40/dio20 rx0 vbat v2p5 reset gnda v3p3a va vb ib ia vref v1 rx1/dio1 gndd xin xout test gndd e_rst/seg32 e_tclk/seg33 seg41/dio21 figure 19 : 68 - pin qfn pinout downloaded from: http:///
78m6612 data sheet ds_6612_001 40 rev 2 5.2.2 package outline d imensions (in mm): *) pin length is nominally 0.4 mm (min. 0.3 mm, max 0.4 mm). **) exposed pad is internally connected to gndd. 0.85 0 downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 41 5.2.3 recommended pcb land pattern for the qfn - 68 package recommended pcb land pattern dimensions symbol description typical dimension e lead pitch 0.4 mm x pad width 0.23 mm y pad length. see n ote 3 . 0.8 mm d see note 1 . 6.3 mm a 6.63 mm g 7.2 mm note 1: do not place unmasked vias in region denoted by dimension d . note 2: soldering of bottom internal pad is not required for proper operation. note 3: the y dimension has been elongated to allow for hand soldering and reworking . production assembly may allow this dimension to be reduced as long as the g dimension is maintained. downloaded from: http:///
78m6612 data sheet ds_6612_001 42 rev 2 6 pin descriptions 6.1 power/ground pins table 27 : power/ground pins name type circuit description gnda p C analog ground: this pin should be connected directly to the ground plane. gndd p C digital ground: this pin should be connected directly to the ground plane. v3p3a p C analog power supply: a 3.3v power supply should be connected to this pin, must be the same voltage as v3p3sys. v3p3sys p C system 3.3 v supply . this pin should be connected to a 3.3 v power supply. v3p3d o 13 auxiliary voltage output of the chip, controlled by the internal 3.3 v selection switch . in mission mode, this pin is internally connected to v3p3sys . in brownout mode, it is internally connected to vbat . this pin is floating in lcd and sleep mode. vbat p 12 battery backup power supply . a battery or super - capacitor is to be connected between vbat and gndd . if no battery is used, connect vbat to v3p3sys. v2p5 o 10 output of the internal 2.5 v regulator . a 0.1 f capacitor to gnda should be connected to this pin. 6.2 analog pins table 28 : analog pins name type circuit description ia, ib i 6 line current sense inputs: these pins are voltage inputs to the internal a/d converter. typically, they are connected to the outputs of current sensors . unused pins must be connected to v3p3a. va, vb i 6 line voltage sense inputs: these pins are voltage inputs to the internal a/d converter . typically, they are connected to the outputs of resistor dividers . unused pins must be connected to v3p3a or tied to the voltage sense input that is in use. v1 i 7 comparator input: this pin is a voltage input to the internal power - fail comparator . the input voltage is compared to the internal bias voltage (1.6 v) . if the input voltage is above vbias, the comparator output will be high (1) . if the comparator output is lower, a voltage fault will occur and the chip will be forced to battery mode. vref o 9 voltage reference for the adc . this pin is normally disabled by setting the vref_cal bit in the i/o ram and can then be left unconnected . if enabled, a 0.1 f capacitor to gnda should be connected. xin xout i 8 crystal inputs: a 32 khz crystal should be connected across these pins . typically, a 27 pf capacitor is also connected from each pin to gnda . it is important to minimize the capacitance between these pins . see the crystal manufacturer datasheet for details. pin types: p = power, o = output, i = input, i/o = input/output the circuit number denotes the equivalent circuit, as specified in section 7 i/o equivalent circuits . downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 43 6.3 digital pins name type circuit description com3, com2, com1, com0 o 5 lcd common outputs: these four pins provide the select signals for the lcd display. seg0seg18 o 5 dedicated lcd segment output pins. seg 14 and seg 15 are only available on the 68 - pin package. seg24/dio4 seg31/dio11 i/o 3, 4, 5 multi - use pins, configurable as either lcd seg driver or dio . (dio4 = sck, dio5 = sda when configured as eeprom interface, wpulse = dio6, varpulse = dio7 when configured as pulse outputs) . if unused, these pins must be configured as dios and set to outputs by the firmware . seg34/dio14 seg37/dio17 , seg39/dio19, seg40/dio20 i/o 3, 4, 5 multi - use pins, configurable as either lcd seg driver or dio . if unused, these pins must be configured as dios and set to outputs by the firmware . seg41/dio21 i/o 3, 4, 5 multi - use pins, configurable as lcd driver or dio (qfn 68 package only) . if un used, this pin must be configured as a dio and set to an output by the firmware . e_rxtx/seg38 e_rst/seg32 i/o 1, 4, 5 multi - use pins, configurable as either emulator port pins (when ice_e pulled high) or lcd seg dr ivers (when ice_e tied to gnd). e_tclk/seg33 o 4, 5 ice_e i 2 ice enable . when zero, e_rst, e_tclk, and e_rxtx become seg32, seg33, and seg38 respectively . for production units, this pin should be pulled to gnd to disable the emulator port . this pin should be brought out to the pro gramming in ter face in order to create a way for reprogramming parts that have the secure bit set. cktest/seg19 o 4, 5 multi - use pin, configurable as either clock pll output or lcd segment driver . can be enabled and disabled by ckout_e[1:0] . tmuxout o 4 digital output test multiplexer . controlled by tmux[ 4:0] . rx1 /dio1 i/o 3, 4, 7 multi - use pin, configurable as uart1 input or general dio . when con - figured as rx1 , this pin can optionally receive a signal from an external photo - detector used in an ir serial interface . if unused, this pin must be terminated to v3p3d or gndd , or configured as a dio and set to an output by the firmware . tx1 /dio2 i/o 3, 4 multi - use pin, configurable as a transmit output from uart1 ( or optionally an optical led transmit output ) , wpulse, rpulse, or general dio . when configured as tx1 , this pin is capable of directly driving an led for transmitting data in an ir serial interface . if unused, this pin must be left open, or config ured as a dio and set to an output by the firmware. dio3 i/o 3, 4 dio pin (qfn 68 package only) reset i 3 this input pin resets the chip into a known state . for normal operation, this pin is connected to gndd . to reset the chip, this pin should be pulled high . no external reset circuitry is necessary. direct connect to ground in normal operation. rx 0 i 3 uart input . if unused, this pin must be terminated to v3p3d or gndd. tx 0 o 4 uart output. test i 7 enables production test . must be grounded in normal operation. pin types: p = power, o = output, i = input, i/o = input/output the circuit number denotes the equivalent circuit, as specified on the following page. downloaded from: http:///
78m6612 data sheet ds_6612_001 44 rev 2 7 i/o equivalent circuits digital input equivalent circuit type 1: standard digital input or pin configured as dio input with internal pull-up gndd 110k v3p3d cmos input v3p3d digital input pin cmos output gndd v3p3d gndd v3p3d digital output equivalent circuit type 4: standard digital output or pin configured as dio output digital output pin lcd output equivalent circuit type 5: lcd seg or pin configured as lcd seg lcd driver gndd lcd seg output pin to mux gnda v3p3a analog input equivalent circuit type 6 : adc input analog input pin comparator input equivalent circuit type 7: comparator input gnda v3p3a to comparator comparator input pin vref equivalent circuit type 9: vref from internal reference gnda v3p3a vref pin v2p5 equivalent circuit type 10: v2p5 from internal reference gndd v3p3d v2p5 pin vbat equivalent circuit type 12: vbat power gndd power down circuits vbat pin v3p3d equivalent circuit type 13: v3p3d from v3p3sys v3p3d pin from vbat 1040 oscillator equivalent circuit type 8: oscillator i/o to oscillator gndd oscillator pin digital input type 2: pin configured as dio input with internal pull-down gndd 110k gndd cmos input v3p3d digital input pin digital input type 3: standard digital input or pin configured as dio input gndd cmos input v3p3d digital input pin downloaded from: http:///
ds_6612_001 78m6612 data sheet rev 2 45 8 ordering information part part description (package, accuracy) flash memory size p ackaging ordering number package marking 78m6612 64 - pin lqfp, 0.5% (lead(pb) - free) 32kb bulk 78m6612 - igt/f 78m6612 - igt 78m6612 64 - pin lqfp, 0.5% (lead(pb) - free) 32kb tape & reel 78m6612 - igtr/f 78m6612 - igt 78m6612 64 - pin lqfp, 0.5% (lead(pb) - free) 32kb * programmed, bulk 78m6612 - igt/f /p 78m6612 - igt 78m6612 64 - pin lqfp, 0.5% (lead(pb) - free) 32kb * programmed, tape & reel 78m6612 - igtr/f /p 78m6612 - igt 78m6612 68 - pin qfn, 0.5% (lead(pb) - free) 32kb bulk 78m6612 - im/f 78m6612 - im 78m6612 68 - pin qfn, 0.5% (lead(pb) - free) 32kb tape & reel 78m6612 - imr/f 78m6612 - im 78m6612 68 - pin qfn, 0.5% (lead(pb) - free) 32kb * programmed, bulk 78m6612 - im/f/p 78m6612 - im 78m6612 68 - pin qfn, 0.5% (lead(pb) - free) 32kb * programmed, tape & reel 78m6612 - imr/f /p 78m6612 - im *contact the factory for more information on programmed part opti ons. 9 contact information for more information about maxim products or to check the availability of the 78m661 3, contact technical support at www.maxim - ic.com/support . downloaded from: http:///
78m6612 data sheet ds_6612_001 46 rev 2 maxim cannot assume responsibility for use of any circuitry other than circui try entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and s pecifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 201 2 maxim integrated products maxim is a registered trademark of maxim integrated products . revision history revision date description 1.0 4/1 /2009 first publication. 1.3 5 /7 /2010 moved firmware specific information to respective developers manuals. added caution to section 1.4.6 : caution. if uart1 is being used for full duplex operation, tx interrupts may be inadvertently cleared and thus a tx safety timer is recommended. added caution to section 1.4.6 about uart0 interrupts. in section 3.10 , changed i/o ram register tx1dis to i/o ram register tx1e . in figure 18 , corrected the name of pin 45 from rx to rx0. 2 1/ 12 added maxim logo. downloaded from: http:///

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